;buildInfoPackage: chisel3, version: 3.4.2, scalaVersion: 2.12.12, sbtVersion: 1.3.10
circuit Router : 
  module Router : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip read_routing_table_request : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>}}, read_routing_table_response : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<32>}, flip load_routing_table_request : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, data : UInt<32>}}, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : UInt<8>, body : UInt<64>}}, outs : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : UInt<8>, body : UInt<64>}}[4]}
    
    cmem tbl : UInt<3>[15] @[Router.scala 51:18]
    io.read_routing_table_request.ready <= UInt<1>("h00") @[Decoupled.scala 72:20]
    io.load_routing_table_request.ready <= UInt<1>("h00") @[Decoupled.scala 72:20]
    io.read_routing_table_response.valid <= UInt<1>("h00") @[Decoupled.scala 56:20]
    io.read_routing_table_response.bits is invalid @[Decoupled.scala 57:19]
    io.read_routing_table_response.bits <= UInt<1>("h00") @[Router.scala 57:39]
    io.in.ready <= UInt<1>("h00") @[Decoupled.scala 72:20]
    wire _io_outs_0_bits_WIRE : {header : UInt<8>, body : UInt<64>} @[Router.scala 60:29]
    _io_outs_0_bits_WIRE.body <= UInt<64>("h00") @[Router.scala 60:29]
    _io_outs_0_bits_WIRE.header <= UInt<8>("h00") @[Router.scala 60:29]
    io.outs[0].bits.body <= _io_outs_0_bits_WIRE.body @[Router.scala 60:14]
    io.outs[0].bits.header <= _io_outs_0_bits_WIRE.header @[Router.scala 60:14]
    io.outs[0].valid <= UInt<1>("h00") @[Decoupled.scala 56:20]
    io.outs[0].bits.body is invalid @[Decoupled.scala 57:19]
    io.outs[0].bits.header is invalid @[Decoupled.scala 57:19]
    wire _io_outs_1_bits_WIRE : {header : UInt<8>, body : UInt<64>} @[Router.scala 60:29]
    _io_outs_1_bits_WIRE.body <= UInt<64>("h00") @[Router.scala 60:29]
    _io_outs_1_bits_WIRE.header <= UInt<8>("h00") @[Router.scala 60:29]
    io.outs[1].bits.body <= _io_outs_1_bits_WIRE.body @[Router.scala 60:14]
    io.outs[1].bits.header <= _io_outs_1_bits_WIRE.header @[Router.scala 60:14]
    io.outs[1].valid <= UInt<1>("h00") @[Decoupled.scala 56:20]
    io.outs[1].bits.body is invalid @[Decoupled.scala 57:19]
    io.outs[1].bits.header is invalid @[Decoupled.scala 57:19]
    wire _io_outs_2_bits_WIRE : {header : UInt<8>, body : UInt<64>} @[Router.scala 60:29]
    _io_outs_2_bits_WIRE.body <= UInt<64>("h00") @[Router.scala 60:29]
    _io_outs_2_bits_WIRE.header <= UInt<8>("h00") @[Router.scala 60:29]
    io.outs[2].bits.body <= _io_outs_2_bits_WIRE.body @[Router.scala 60:14]
    io.outs[2].bits.header <= _io_outs_2_bits_WIRE.header @[Router.scala 60:14]
    io.outs[2].valid <= UInt<1>("h00") @[Decoupled.scala 56:20]
    io.outs[2].bits.body is invalid @[Decoupled.scala 57:19]
    io.outs[2].bits.header is invalid @[Decoupled.scala 57:19]
    wire _io_outs_3_bits_WIRE : {header : UInt<8>, body : UInt<64>} @[Router.scala 60:29]
    _io_outs_3_bits_WIRE.body <= UInt<64>("h00") @[Router.scala 60:29]
    _io_outs_3_bits_WIRE.header <= UInt<8>("h00") @[Router.scala 60:29]
    io.outs[3].bits.body <= _io_outs_3_bits_WIRE.body @[Router.scala 60:14]
    io.outs[3].bits.header <= _io_outs_3_bits_WIRE.header @[Router.scala 60:14]
    io.outs[3].valid <= UInt<1>("h00") @[Decoupled.scala 56:20]
    io.outs[3].bits.body is invalid @[Decoupled.scala 57:19]
    io.outs[3].bits.header is invalid @[Decoupled.scala 57:19]
    node _T = and(io.read_routing_table_request.valid, io.read_routing_table_response.ready) @[Router.scala 65:44]
    when _T : @[Router.scala 65:85]
      io.read_routing_table_request.ready <= UInt<1>("h01") @[Decoupled.scala 65:20]
      node _T_1 = bits(io.read_routing_table_request.bits.addr, 3, 0) @[Router.scala 66:43]
      infer mport MPORT = tbl[_T_1], clock @[Router.scala 66:43]
      io.read_routing_table_response.valid <= UInt<1>("h01") @[Decoupled.scala 47:20]
      io.read_routing_table_response.bits <= MPORT @[Decoupled.scala 48:19]
      skip @[Router.scala 65:85]
    else : @[Router.scala 70:50]
      when io.load_routing_table_request.valid : @[Router.scala 70:50]
        io.load_routing_table_request.ready <= UInt<1>("h01") @[Decoupled.scala 65:20]
        node _T_2 = bits(io.load_routing_table_request.bits.addr, 3, 0) @[Router.scala 72:8]
        infer mport MPORT_1 = tbl[_T_2], clock @[Router.scala 72:8]
        MPORT_1 <= io.load_routing_table_request.bits.data @[Router.scala 72:19]
        node _T_3 = bits(reset, 0, 0) @[Router.scala 73:11]
        node _T_4 = eq(_T_3, UInt<1>("h00")) @[Router.scala 73:11]
        when _T_4 : @[Router.scala 73:11]
          printf(clock, UInt<1>(1), "setting tbl(%d) to %d\n", io.load_routing_table_request.bits.addr, io.load_routing_table_request.bits.data) @[Router.scala 73:11]
          skip @[Router.scala 73:11]
        skip @[Router.scala 70:50]
      else : @[Router.scala 75:26]
        when io.in.valid : @[Router.scala 75:26]
          node _idx_T = bits(io.in.bits.header, 4, 0) @[Router.scala 77:29]
          node _idx_T_1 = bits(_idx_T, 3, 0) @[Router.scala 77:18]
          infer mport idx = tbl[_idx_T_1], clock @[Router.scala 77:18]
          node _T_5 = bits(idx, 1, 0)
          when io.outs[_T_5].ready : @[Router.scala 78:30]
            io.in.ready <= UInt<1>("h01") @[Decoupled.scala 65:20]
            node _T_6 = bits(idx, 1, 0)
            io.outs[_T_6].valid <= UInt<1>("h01") @[Decoupled.scala 47:20]
            io.outs[_T_6].bits.body <= io.in.bits.body @[Decoupled.scala 48:19]
            io.outs[_T_6].bits.header <= io.in.bits.header @[Decoupled.scala 48:19]
            node _T_7 = bits(io.in.bits.header, 3, 0) @[Router.scala 81:108]
            infer mport MPORT_2 = tbl[_T_7], clock @[Router.scala 81:108]
            node _T_8 = bits(reset, 0, 0) @[Router.scala 81:13]
            node _T_9 = eq(_T_8, UInt<1>("h00")) @[Router.scala 81:13]
            when _T_9 : @[Router.scala 81:13]
              printf(clock, UInt<1>(1), "got packet to route header %d, data %d, being routed to out(%d)\n", io.in.bits.header, io.in.bits.body, MPORT_2) @[Router.scala 81:13]
              skip @[Router.scala 81:13]
            skip @[Router.scala 78:30]
          skip @[Router.scala 75:26]
    
